MIPI Demo Day Taipei 2026
21 October 2026
Education Sessions
教育研討會
In addition to the 16 member companies showcasing their innovative solutions, MIPI Demo Day Taipei will also deliver education presented by MIPI working group chairs and technical experts. These four sessions will diving into the latest developments and a look ahead at what's next for MIPI Display, A-PHY®, SWI3S®, and I3C®.
除了 16 家 MIPI 會員公司將於活動現場展示創新解決方案外,當日也將舉辦四場教育研討會,由 MIPI 工作小組主席與技術專家到場分享,深入探討 MIPI Display、A-PHY®、SWI3S® 及 I3C® 的最新發展與未來方向。
MIPI I3C Developments and New MIPI Specification for I/Os Over I3C Bridge
Presenters: Eyuel Zewdu Teferi, Aruni Nelson
10:30-11:15 a.m.
The first part of this presentation will provide an update on the latest developments in MIPI I3C®, covering advanced features such as HDR modes, multilane communication, target reset and I²C backward compatibility. It will also preview upcoming I3C v1.3 enhancements, including extended-length buses, multi-bus bridging, data protection and functional safety, highlighting the new applications they enable.
The second part of the presentation will introduce the forthcoming MIPI Specification for I/Os Over I3C Bridge. The new specification will standardize the bridging of I²C, SPI, UART and GPIO interfaces over MIPI I3C to reduce pin count, simplify system design, improve interoperability and extend the life of existing peripheral devices. This part will conclude with a look ahead at future deliverables from the MIPI I/O Bridges Working Group.
MIPI I3C發展暨最新 I/Os over I3C橋接規格
講者:Eyuel Zewdu Teferi、Aruni Nelson
上午10:30–11:15
研討會第一部分將帶來 MIPI I3C® 最新發展,介紹包含 HDR 模式、多通道通訊、目標裝置重置與 I²C 向下相容性等進階功能。
同時也將搶先介紹將於 I3C v1.3 導入的強化功能,包括延伸匯流排長度、多匯流排橋接、資料保護與功能安全,並說明這些新功能可望支援的應用情境。
第二部分將介紹即將推出的 MIPI I/Os Over I3C 橋接規格。
這項新規格將建立MIPI I3C 橋接 I²C、SPI、UART 與 GPIO 介面的標準化機制,可協助系統開發人員減少接腳數量、簡化系統設計、提升互通性,並延長既有周邊裝置的使用壽命。
最後,講者也將分享 MIPI I/O Bridges工作小組後續規劃,以及未來預計推出的相關技術成果。
Presenters
講者
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Eyuel Zewdu Teferi
Chair, MIPI I3C Working Group
Senior Staff Engineer, STMicroelectronicsEyuel Zewdu has been with STMicroelectronics since 2016 and is currently a senior staff engineer focusing on front-end digital design in STM’s MEMS sensor division. He has worked on projects defining, designing, implementing and validating communication interfaces for MEMS sensors. He earned his master's degree in electronics engineering from Politecnico di Torino. He is involved in both MIPI and JEDEC, and is currently the chair of the MIPI I3C and I3C Basic Ad Hoc working groups.
MIPI I3C 工作小組主席
意法半導體資深工程師Eyuel Zewdu Teferi 自 2016 年加入意法半導體,目前擔任資深工程師,主要負責MEMS 感測器事業的前端數位設計。過往曾參與多項 MEMS 感測器通訊介面的規格定義、設計、實作與驗證專案。Eyuel 擁有義大利杜林理工大學(Politecnico di Torino)電子工程碩士學位,並參與 MIPI 聯盟與全球固態技術協會(JEDEC)的技術標準工作,目前擔任 MIPI I3C與 I3C Basic 專案工作小組主席。
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Aruni Nelson
Chair, MIPI I/O Bridges Working Group
Principal Engineer, Intel CorporationAruni is a principal engineer at Intel Corporation, focused on high-speed and low-speed IO architecture and technology development, including debug software architecture. She has contributed to several industry standard specifications for next generation IO and debug technologies in multiple open standards forums. At MIPI, she chairs the Audio and I/O Bridges working groups, and leads the development of future debug specifications (e.g., Debug Over PCIe and Debug Over UCIe). Aruni also serves as the co-vice chair of the I3C Working Group. A gold medalist from Bangalore University in India, she holds a bachelor of engineering degree and brings broad expertise in developing technology products—from client PC and mobile devices, to medical imaging systems, and broadcasting switching and routing equipment.
MIPI I/O 橋接工作小組主席
英特爾主任工程師Aruni Nelson 現任英特爾主任工程師,專注於高速與低速 I/O 架構、相關技術開發及除錯軟體架構。曾參與多個開放標準組織,投入下一代 I/O 與除錯技術的產業標準制定。在 MIPI 聯盟中,Aruni 擔任音訊工作小組及 I/O 橋接工作小組主席,並主導未來除錯規格的開發,包括PCIe 除錯規格(Debug Over PCIe)與 UCIe 除錯規格(Debug Over UCIe);同時也擔任 I3C 工作小組共同副主席。Aruni 畢業於印度班加羅爾大學,並以優異成績獲頒金牌獎,取得工程學士學位。Aruni 擁有豐富的技術產品開發經驗,涵蓋用戶端 PC、行動裝置、醫療影像系統,以及廣播訊號交換與路由設備等領域。
MIPI A-PHY: New Compliance Program and Recent Specification Developments
Presenters: Edo Cohen, Tom Kopf
11:15 a.m.–12 p.m.
This presentation will provide the latest insights into the MIPI A-PHY® specification and the new MIPI A-PHY Compliance Program, which supports its continued industry adoption. The session will begin with an overview of the latest developments in MIPI’s high-speed, long-reach SerDes interface, including the release of A-PHY v2.1. It will highlight key advances across the A-PHY ecosystem, including growing industry adoption, strategic collaborations and emerging implementations. Next, the presentation will introduce the MIPI A-PHY Compliance Program, explaining its structure, processes and benefits. Attendees will learn how transmitter and receiver physical layer testing supports broader industry adoption and enables the reliable, scalable deployment of A-PHY-enabled devices in automotive architectures.
The presentation will conclude with an opportunity for attendees to engage with the speakers and discuss the latest developments in the A-PHY ecosystem.
MIPI A-PHY:全新相容性認證計畫與近期規格發展
講者:Edo Cohen、Tom Kopf
上午 11:15–中午 12:00
本場研討會將深入介紹 MIPI A-PHY® 規格的近期發展,以及全新的 MIPI A-PHY 相容性認證計畫,推動 A-PHY 在產業中的持續導入。內容將涵蓋 MIPI 高速、長距離 SerDes 介面的最新發展,包括近期發布的 A-PHY v2.1,並分享 A-PHY 生態系的重要進展,如產業採用持續成長、策略合作,以及新興應用與實作案例。研討會也將說明 MIPI A-PHY 相容性認證計畫的架構、流程與效益,並探討如何透過傳送端與接收端的實體層測試,提升產品互通性與可靠度,進一步支援 A-PHY 裝置在車用架構中的可靠且可擴展部署。活動最後將安排交流時間,讓與會者可直接與講者討論 A-PHY 生態系的最新技術與產業發展。
Presenters
講者
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Edo Cohen
Co-Chair, MIPI A-PHY Working Group
Vice Chair, MIPI Technical Steering Group
VP Automotive Products, Valens SemiconductorEdo has more than three decades of experience as a senior system engineer, with extensive expertise in system architecture, technical specifications and project implementation. Prior to joining Valens, Edo worked as a senior system architect at Intel Corporation, leading efforts in the wearables and IoT division. He has also held senior staff system engineer roles at Marvell Cellular Division, overseeing the company's cellular processor environment, as well as engineering managerial positions at Floware, Alvarion, and NAMS. Edo holds an MBA and a bachelor of science degree in electrical engineering from Tel Aviv University.
MIPI A-PHY 工作小組共同主席
MIPI 技術指導小組副主席
Valens Semiconductor 車用產品副總裁
Edo Cohen 擁有超過 30 年的系統工程經驗,專精於系統架構、技術規格制定與專案執行。在加入 Valens Semiconductor 前,曾擔任英特爾資深系統架構師,主導穿戴式裝置及 IoT 事業相關技術專案。Edo 亦曾在 Marvell Cellular Division 擔任資深高級系統工程師,負責行動通訊處理器相關系統,也曾於 Floware、Alvarion 與 NAMS 擔任工程管理職務。Edo擁有特拉維夫大學(Tel Aviv University)MBA 與電機工程理學士學位。 -
Tom Kopf
Chair, MIPI A-PHY Compliance Advisory Group
COO, BitifEye GmbHAfter earning his MBA in 1999, Tom started at a PCB manufacturer as an account manager, and exiting as a manager, customer service, and deputy sales manager in 2012. After a two-year period as managing director, Stadtmarketing Böblingen e.V, Tom joined BitifEye Digital Test solution in 2015. He is currently leading the development of the A-PHY compliance program for MIPI Alliance.
MIPI A-PHY相容性認證諮詢小組主席
BitifEye GmbH 營運長Tom Kopf 於 1999 年取得 MBA 學位後,進入 PCB 製造商擔任客戶經理,並在任職期間累積客戶服務與業務管理經驗,至 2012 年離開該公司。其後,他曾擔任 Stadtmarketing Böblingen e.V. 執行總監兩年,並於 2015 年加入 BitifEye Digital Test Solutions。目前 Tom 主要負責推動 MIPI 聯盟 A-PHY 相容性認證計畫的開發工作。
Exploring MIPI SWI3S: Features, Applications, Tools and What's Next
Presenter: Aruni Nelson
1:30–2:15 p.m.
The MIPI SWI3S® v1.0 specification defines a low-latency, multi-drop audio interconnect with bandwidth up to 76 Mbps, supporting both single-ended and differential-low-voltage signaling modes through a unified protocol and software stack. Designed for applications ranging from compact wearables to automotive and robotics, the specification features low-voltage, embedded-clock signaling for reduced EMI/EMC and long cable support.
This presentation will cover SWI3S use cases, architecture, protocols, command flows and key improvements over existing audio interfaces. It will also provide an overview of supporting tools such as the SWI3S visualizer and a preview of the forthcoming Audio Bus Controller Interface (ABCI) and planned enhancements expected in SWI3S v1.1.
MIPI SWI3S技術解析:功能、應用、工具與未來發展
講者:Aruni Nelson
下午 1:30–2:15
MIPI SWI3S® v1.0 定義了一套低延遲、多點連接(Multi-drop)的音訊互連介面,頻寬最高可達 76 Mbps,透過統一的協定與軟體堆疊,同時支援單端與差動低電壓訊號模式。SWI3S 可應用於從小型穿戴式裝置到汽車與機器人系統等多種情境。採用低電壓及嵌入式時脈訊號設計,有助於降低 EMI/EMC,同時支援較長距離的纜線連接。本場研討會將深入介紹 SWI3S 的應用情境、架構、協定與指令流程,並解析相較於現有音訊介面的主要技術改進。講者也將分享 SWI3S Visualizer 等相關支援工具,搶先介紹即將推出的 Audio Bus Controller Interface(ABCI),以及預計於 SWI3S v1.1 導入的後續強化功能。
Presenter
講者
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Aruni Nelson
Chair, MIPI Audio Working Group
Principal Engineer, Intel CorporationAruni is a principal engineer at Intel Corporation, focused on high-speed and low-speed IO architecture and technology development including debug software architecture. She has contributed to several industry standard specifications for next generation IO and debug technologies in multiple open standards forums. At MIPI, she chairs the Audio and IO Bridges working groups, and leads the development of future debug specifications (e.g., Debug Over PCIe and Debug Over UCIe). Aruni also serves as the co-vice chair of the I3C Working Group. A gold medalist from Bangalore University in India, she holds a bachelor of engineering degree and brings broad expertise in developing technology products from client PC and mobile devices, to medical imaging systems, and broadcasting switching and routing equipment.
MIPI 音訊工作小組主席
英特爾主任工程師Aruni Nelson 現任英特爾主任工程師,專注於高速與低速 I/O 架構、相關技術開發及除錯軟體架構。曾參與多個開放標準組織,投入下一代 I/O 與除錯技術的產業標準制定。在 MIPI 聯盟中,Aruni 擔任音訊工作小組及 I/O 橋接工作小組主席,並主導未來除錯規格的開發,包括PCIe 除錯規格(Debug Over PCIe)與 UCIe 除錯規格(Debug Over UCIe);同時也擔任 I3C 工作小組共同副主席。Aruni 畢業於印度班加羅爾大學,並以優異成績獲頒金牌獎,取得工程學士學位。Aruni 擁有豐富的技術產品開發經驗,涵蓋用戶端 PC、行動裝置、醫療影像系統,以及廣播訊號交換與路由設備等領域。
What's Coming in MIPI DSI-2 v3.0 and DCS v3.0
Presenter: Samson Kim
2:15–3 p.m.
The upcoming releases of MIPI DSI-2™ v3.0 and MIPI DCS™ v3.0 will introduce new capabilities for next-generation displays, with a focus on low-power operation and emerging AR applications. This session presents the latest enhancements, including partial update in video mode, field-sequential display support, command mode peripheral sync synchronization, frame synchronized single wire peripheral to host (P2H) sideband interface, line group sequential support, multipoint support, and new DCS commands for partially refreshed displays.
The presentation will provide insight into the technical motivation, implementation considerations and benefits of these new features, explaining how they can enable more efficient display architectures in preparation for AR- and 6G-ready applications.
搶先看 MIPI DSI-2 v3.0 與 DCS v3.0 最新功能
講者:Samson Kim
下午 2:15-3:00
即將推出的 MIPI DSI-2™ v3.0 與 MIPI DCS™ v3.0,將為下一代顯示系統導入多項新功能,重點涵蓋低功耗運作與新興 AR 應用。本場研討會將介紹最新規格強化內容,包括:視訊模式下的局部更新、場序式顯示(Field-Sequential Display)支援、命令模式周邊裝置同步、影格同步單線式周邊裝置至主機旁帶介面、線群循序(Line Group Sequential)支援、多點連接支援、針對局部更新顯示器新增的 DCS 指令。講者將進一步說明新功能背後的技術設計考量、實作考量與效益,並解析如何協助打造更有效率的顯示架構,為未來 AR 與 6G 應用做好準備。
Presenter
講者
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Samson Kim
Chair, MIPI Display Working Group
Senior Director of Engineering, Qualcomm Inc.
Samson Kim is a senior engineering leader with more than 25 years of experience in semiconductor and display technology. He currently serves as senior director of engineering at Qualcomm, leading a global team developing advanced display IP, high-speed display interfaces and industry standards across mobile, automotive, computing, IoT and XR platforms.MIPI 顯示器工作小組主席
高通資深工程總監Samson Kim在半導體與顯示技術領域擁有超過 25 年經驗。現任高通資深工程總監,帶領全球團隊開發先進顯示 IP、高速顯示介面與相關產業標準,應用涵蓋行動裝置、汽車、運算、IoT 與 XR 平台。


