Abstract: In the fast-growing mobile industry, there is a constant need of reducing the sizes of mobile chips, which is accomplished by reducing the number of pin connections in a chipset. SPMI protocol plays a vital role in doing so, as it supports multi-master and multi-slave systems. It is generally used to send transactions between the processor and the PMICs. There are occasions where the processor is in sleep, but the inter-PMIC communication exists. This motivation has led to the requirement of multiple SPMI masters – one on the processor and other on the PMIC. Since, the processor and the PMICs exist as different chips, there is a challenge to verify the multiple masters. A system-level test bench is required where both the masters are instantiated. The major verification efforts lie in validating the scenarios like multiple masters waking up at the same time and trying to connect, second master trying to connect when one master is already present, multiple masters and slaves arbitrating with different priority levels, BOM (Bus Owner Master) transfer, disconnection of a master using TBO (Transfer Bus Operation) or during hard reset or during command parity error, noise injection during various phases of a transaction and recovery after it, watchdog timer expiry and internal reset in the slave when SPMI clock is stopped abruptly during a transaction. Our paper elaborates on the multi-master multi-slave test bench and how the verification challenges were handled and closed.
Sanjeev Kumar has around 8+ years of industry experience in ASIC Design Verification and is working with Qualcomm as a Senior Lead Engineer. He has expertise in the verification of peripheral IPs (SPMI, PMIC Arbiter), Ethernet IPs (MAC, Port) and Point-of-Sale (PoS) IPs. He has extensively worked in constraint random verification using System Verilog and UVM-based verification environment. He has done B.E. from BITS-Pilani and his hobbies are traveling, playing cricket/badminton and watching movies/TV series.
Purva Joshi has around 4+ years of industry experience in ASIC Design Verification and is working with Qualcomm as an Engineer. She has experience in IP as well as SOC verification. She has expertise in formal verification. She holds a B.E. degree and her hobbies are playing badminton, gardening, watching movies.
Ritesh Jain has around 16+ years of experience and is working with Qualcomm as a Senior Staff Engineer/Manager. He has an extensive experience in IP/CPU/Multi processor/SOC verification. He champions in the field of low power verification and mixed signal verification. He is a pass out of BITS-Pilani and has hobby as Painting.