MIPI I3C Plugfest
Taipei, Taiwan
19-21 October 2026
MIPI I3C/I3C Basic Testing Details
Platform: Standardized cabling (.1 inch spacing – female-female wires, GND, SDA, GND, SCL, GND). Legacy I2C device allowed. Power supply may be needed for targets. 1.8v and 3.3v devices present.
Features under Test:
- Pure and Legacy I3C SDR Read/Write
- I3C SDR Read/Write
- Dynamic Address Assignment (including SETDASA and RSTDAA)
- IBI with/without MDB – if supported
- Basic Direct CCC’s
- Enter/Exit HDR (for SDR only devices)
- DDR Read/Write/CRC – if supported
- TSP Read/Write – if Target supported
- Controller/Target Error Handling
- Multi-Target Topologies (at least two I3C devices) – After confirmed point-to-point functionality
- Include Direct/Broadcast CCC’s
- HCI v1.0 related tests – to ensure a hardware and standard software compatibility
- Timing Control
- Sync Mode
- Async Mode 0/1 and Async Mode Exit
- Secondary Controller/Main Controller Handoff – if supported
- Target Reset
- Multilane features
- 1.2V support for devices that are supporting it
- Group Addressing
- Any other I3C v1.1.1 and I3C Basic v1.1.1 capabilities supported
Test Equipment: Test companies may bring oscilloscopes with I3C protocol Trigger and Decode analysis and active probes
Other: Device Characteristics Register (DCR) assignments are available for each I3C Target
I3C Physical Interface
- Objective: Maintain a consistent physical interconnect of design and length for easy interoperation between varied test PCBs and typical I3C functionality
- Design: 0.1 inch spacing female to female AWG 26 ribbon cable with solderless individual connectors.
- Pinout: GND, SDA, GND, SCL, GND
- Length: Max 15cm (0.02Ohm, 2.5pf)
- Example: https://www.amazon.com/dp/B01L5ULRUA?psc=1
I3C Conformance Test Suite for I3C/I3C Basic v1.2
A conformance test suite (CTS) has been developed to improve the interoperability of products that adopt the MIPI I3C interface. It defines a set of conformance or interoperability tests whereby products can be tested against other implementations of the I3C or I3C Basic v1.2 specifications. The latest version of the CTS focuses on SDR-only devices without optional I3C capabilities, all controller and target error detection and recovery methods, and basic HDR Enter/Tolerance/Restart/Exit in scope, with HDR-DDR under consideration.
MIPI IOs Over I3C Bridge
Members developing devices, bridges, adapters, analyzers, or validation tools implementing the MIPI IOs over I3C Bridge Specification DRAFT v0.6 r01 (or newer) are encouraged to participate in this Plugfest.
The IOs over I3C Bridge track provides an opportunity for early interoperability testing between implementations, helping participants validate protocol behavior, bridge functionality, software compatibility, and system-level integration before broader ecosystem deployment. Areas of interest may include:
- Bus initialization and bridge device discovery flows
- Register access / bridge configuration
- Protocol-specific transactions with downstream devices
- Interrupt/event handling
- Multi-device interoperability
- Timing and synchronization behavior
- Error handling and recovery
Participants are encouraged to bring both hardware and software implementations where possible, including host-side drivers, firmware, analyzers, or debugging tools to accelerate issue identification and interoperability validation.
Implementers should follow the I3C physical interface guidance defined above for interoperability between platforms and test setups.


